A SIMPLIFIED SVPWM METHOD TO REDUCE COMMON-MODE VOLTAGE FOR VOLTAGE SOURCE INVERTER
DOI:
https://doi.org/10.62985/j.huit_ojs.vol26.no2E.382Keywords:
Space-vector PWM, Carrier-based PWM, Common-mode voltage suppression, Voltage-source inverterAbstract
This study introduces a hybrid space vector pulse width modulation strategy aimed at mitigating common-mode voltage (CMV) in voltage source inverters. The proposed approach integrates the characteristics of Near-State PWM (NSPWM) and Active Zero-State PWM (AZSPWM) within a unified modulation framework. The space-vector diagram is partitioned into four operating regions, where only active voltage vectors are utilized for modulation. To enable practical implementation, a simplified carrier-based realization is developed using two triangular carriers with a 180° phase displacement. An offset formulation is derived for each operating region of the reference vector to generate the required switching signals. Compared with the conventional 120° phase-shifted carrier PWM technique, the proposed scheme significantly suppresses CMV across the entire space-vector plane. In addition, incorporating the NSPWM concept reduces switching transitions, leading to lower switching power losses and improved overall efficiency. The effectiveness of the modulation strategy is verified through simulation studies conducted in MATLAB/Simulink and PLECS. The results confirm that the proposed technique achieves effective CMV suppression while maintaining a simple implementation structure, making it suitable for digital control platforms with limited computational resources.
References
[1] H. Chen and H. Zhao, ‘Review on pulse-width modulation strategies for common-mode voltage reduction in three-phase voltage-source inverters’, Nov. 16, 2016, Institution of Engineering and Technology. doi: https://doi.org/10.1049/iet-pel.2015.1019.
[2] E. Robles, M. Fernandez, J. Andreu, E. Ibarra, and U. Ugalde, ‘Advanced power inverter topologies and modulation techniques for common-mode voltage elimination in electric motor drive systems’, Apr. 01, 2021, Elsevier Ltd. doi: https://doi.org/10.1016/j.rser.2021.110746.
[3] Y. Huang et al., ‘Analytical characterization of CM and DM performance of three-phase voltage-source inverters under various PWM patterns’, IEEE Trans. Power Electron., vol. 36, no. 4, pp. 4091–4104, 2021, doi: https://doi.org/10.1109/TPEL.2020.3024836.
[4] H. Qamar, H. Qamar, and R. Ayyanar, ‘Performance Analysis and Experimental Validation of 240°-Clamped Space Vector PWM to Minimize Common Mode Voltage and Leakage Current in EV/HEV Traction Drives’, IEEE Trans. Transp. Electrif., vol. 8, no. 1, pp. 196–208, 2022, doi: https://doi.org/10.1109/TTE.2021.3108957.
[5] A. M. Hava and E. Ün, ‘Performance analysis of reduced common-mode voltage PWM methods and comparison with standard PWM methods for three-phase voltage-source inverters’, IEEE Trans. Power Electron., vol. 24, no. 1, pp. 241–252, 2009, doi: https://doi.org/10.1109/TPEL.2008.2005719.
[6] C. C. Hou, C. C. Shih, P. T. Cheng, and A. M. Hava, ‘Common-mode voltage reduction pulsewidth modulation techniques for three-phase grid-connected converters’, IEEE Trans. Power Electron., vol. 28, no. 4, pp. 1971–1979, Apr. 2013, doi: https://doi.org/10.1109/TPEL.2012.2196712.
[7] S. K. Mun and S. Kwak, ‘Reducing common-mode voltage of three-phase VSIs using the predictive current control method based on reference voltage’, J. Power Electron., vol. 15, no. 3, pp. 712–720, Jan. 2015, doi: https://doi.org/10.6113/JPE.2015.15.3.712.
[8] A. Janabi and B. Wang, ‘Hybrid SVPWM Scheme to Minimize the Common-Mode Voltage Frequency and Amplitude in Voltage Source Inverter Drives’, IEEE Trans. Power Electron., vol. 34, no. 2, pp. 1595–1610, Feb. 2019, doi: https://doi.org/10.1109/TPEL.2018.2834409.
[9] X. Wu, G. Tan, Z. Ye, Y. Liu, and S. Xu, ‘Optimized common-mode voltage reduction PWM for three-phase voltage-source inverters’, IEEE Trans. Power Electron., vol. 31, no. 4, pp. 2959–2969, 2016, doi: https://doi.org/10.1109/TPEL.2015.2451673.
[10] J. Lee and J. W. Park, ‘Selection of PWM Methods for Common-Mode Voltage and DC-Link Capacitor Current Reduction of Three-Phase VSI’, IEEE Trans. Ind. Appl., vol. 59, no. 1, pp. 1064–1076, 2023, doi: https://doi.org/10.1109/TIA.2022.3213632.
[11] M. Wei, S. Huang, G. Liang, W. Liao, X. Wu, and S. Huang, ‘An Optimal PWM Method With Reduced Common-Mode Voltage and Current Ripple for Three-Phase Voltage-Source Inverter’, IEEE Trans. Transp. Electrif., vol. 11, no. 2, pp. 6799–6811, 2025, doi: https://doi.org/10.1109/TTE.2024.3516118.
[12] J. W. Kimball and M. Zawodniok, ‘Reducing common-mode voltage in three-phase sine-triangle PWM with interleaved carriers’, IEEE Trans. Power Electron., vol. 26, no. 8, pp. 2229–2236, 2011, doi: https://doi.org/10.1109/TPEL.2010.2092791.


